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sdc-14560 description the sdc-14560 is a series of high-reli- ability synchro or resolver-to-digital (s/r-d) converters with user-program- mable resolution of 10, 12, 14, or 16 bits. other features of the sdc-14560 are high-quality velocity output and her- metic seal. user-programmable resolution has been designed into the sdc-14560 to increase the capabilities of modern motion control systems. the precise positioning attained at 16-bit resolu- tion and fast tracking of a 10-bit device are now available from one 36- pin double dip hybrid. velocity output (vel) from the sdc-14560 is a ground-based voltage of 0 to 10 vdc with a linearity to 0.7%. output voltage is positive for an increasing angle. the sdc-14560 series accepts broadband inputs: 360 hz to 1 khz, or 47 hz to 1 khz. the digital angle out- put from the sdc-14560 is a natural binary code, parallel positive logic and is ttl/cmos compatible. synchronization to a computer is accomplished via a converter busy (cb) and an inhibit (inh) input. applications because of its high reliability, accura- cy, small size, and low power con- sumption, the sdc-14560 is ideal for the most stringent and severe indus- trial and military ground or avionics applications. all models are available with mil-prf-38534 processing as a standard option. designed with three-state output, the sdc-14560 is especially well suited for use with computer-based systems. among the many possible applica- tions are radar and navigation sys- tems, fire control systems, flight instrumentation, and flight trainers or simulators. synchro-to-digital converter features ? programmable resolution: 10, 12, 14 or 16 bits high-quality velocity output eliminates tachometer accuracy to 1.3 arc minutes small size synchro or resolver input synthesized reference eliminates 180 lock-up ct mode s1 s2 s3 solid state synchro input option electronic scott t sin cos s1 s2 s3 solid state resolver input option sin cos s4 solid state resolver input option sin cos sin cos input options v internal dc reference reference conditioner synthesized ref demod bit detect error processor high accuracy control transformer input option 16-bit ct transparent latch 16-bit output transparent latch 3 state ttl buffer 3 state ttl buffer 16-bit u-d counter edge triggered latch vco inhibit transparent latch power supply conditioner digital angle +5 v inh em bits 1-8 bits 9-16 el s resolution control t 50 ns delay 0.4-1 s +10 v internal dc ref v (+5 v) +15 inh cb vel e bit +15 v -15 v diff gain of 2 diff gain of 2, 7 vel u t e d r u t gain e sin ( - ) 1 lsb antijitter feedback ref in rl rh sin cos q ab resolver conditioner voltage follower buffer ? 1987, 1999 data device corporation figure 1. sdc-14560 block diagram
2 data device corporation www.ddc-web.com sdc-14560/q-10/03-0 table 1. sdc-14560 specifications apply over temperature range power supply range reference frequency and amplitude ranges; 10% signal amplitude variation; and up to 10% harmonic distortion in the reference. parameter unit value resolution (1) accuracy (2) repeatability differential linearity bits min lsb lsb 10, 12, 14, or 16 6, 4, 2, or 1 +1lsb 1 max 1 max in the 16th bit reference input characteristics carrier frequency ranges nominal 400 hz units nominal 60 hz units voltage range input impedance single ended differential common mode range hz hz vrms ohm ohm v 360-1000 47-1000 4-130 250k min 500k min 210 peak max 500 transient peak signal input characteristics (voltage options and minimum input impedance balanced) synchro zin line to line zin each line to gnd resolver zin single ended zin differential zin each line to gnd common mode range direct (1.0 vl-l) input signal type sin/cos voltage range max voltage w/o damage input impedance ohm ohm ohm ohm ohm v vrms ohm 11.8 vl-l 90 vl-l 17.5k 130k 11.5k 85k 11.8 vl-l 26 vl-l 23k 50k 46k 100k 23k 50k 60 max 60 max sin and cos resolver signals referenced to converter inter- nal dc reference v. 1 v nominal, 1.15 v max 15 v continuous 100 v peak transient zin > 20m//10 pf voltage follower reference synthesizer sig/ref phase shift deg 60 max, 45 typ digital input/output logic type inputs inhibit (inh) enable bits 1 to 8 (em) enable bits 9 to 16 (el) s (control transformer) resolution control (a & b) (unused output data bits are set to 0) ttl/cmos compatible logic 0 = 0.8 v max logic 1 = 2.0 v min loading = 30 a max p.u. current source to +5 v//5 pf max cmos transient protected logic 0 inhibits data stable after 0.5 s logic 0 enables logic 1 high z logic 0 enables logic 1 high z logic 0 for use as ct b a resolution 0 0 10 bits 0 1 12 bits 1 0 14 bits 1 1 16 bits table 1. sdc-14560 specifications (contd) parameter unit value output parallel data converter busy (cb) bit drive capability bits 10, 12, 14, or 16 parallel lines; natural binary angle, positive logic 0.4 to 1 s positive pulse; leading edge initiates counter update. logic 0 for fault. 50 pf plus rated logic drive. logic 0; 1 ttl load, 1.6 ma at 0.4 vmax logic 1; 10 ttl loads 0.4 ma at 2.8 v min high z; 10 a//5 pf max logic 0; 100 mv max driving cmos logic 1; +5 v supply minus 100 mv min driving cmos analog outputs velocity (vel) ac error (e) load mv rms kohm see tables 3 and 4 50 per lsb of error (10-bit mode) 25 per lsb of error (12-bit mode) 12.5 per lsb of error (14-bit mode) 6.3 per lsb of error (16-bit mode) 3 min dynamic characteristics see table 3. power supply characteristics nominal voltage voltage range max voltage w/o damage current % v ma max +15 v +5 v -15 v 5105 +18 +8 -18 25 10 15 thermal resistance junction to case, jc junction to ambient, ja temperature ranges operating -30x -10x storage c/w c/w c c c 8 20 0 to +70 -55 to +125 -65 to +150 physical characteristics size weight in. (mm) oz. (g) 1.9 x 0.78 x 0.21 (48.3 x 19.8 x 5.3) 36-pin double dip 0.7 max (20) transformers characteristics (see ordering information for list of transformers. reference transformers are optional for both solid-state and voltage follower input options.) 400 hz transformers reference transformer carrier frequency range voltage range input impedance breakdown voltage to gnd 360 - 1000 hz 18 - 130 v 40 k ? min 1200 v peak
introduction the circuit shown in figure 1, the sdc-14560 block diagram, consists of three main parts: the signal input; a feedback loop, whose elements are the control transformer, demodulator, error processor, vco and up-down counter; and digital interface cir- cuitry including various latches and buffers. signal inputs the sdc-14560 series offers three input options: synchro, resolver, and direct. in a synchro or resolver, shaft angle data is transmitted as the ratio of carrier amplitudes across the input ter- minals. synchro signals, which are of the form sin cos t, sin( + 120)cos t, and sin( + 240)cos t are internally con- verted to resolver format; sin cos t and cos cos t. direct inputs accept 1 vrms inputs in resolver form, (sin cos t and cos ? cos t) and are buffered prior to conversion. figure 2 illustrates synchro and resolver signals as a function of the angle . the solid state signal and reference inputs are true differential inputs with high ac and dc common mode rejection. input impedance is maintained with power off. 3 data device corporation www.ddc-web.com sdc-14560 q-10/03-0 table 1. sdc-14560 specifications (contd) parameter unit value transformers characteristics (contd) signal transformer carrier frequency range breakdown voltage to gnd minimum input impedances (balanced) 90 v l-l 26 v l-l 11.8 v l-l 60 hz transformers reference transformer carrier frequency range input voltage range input impedance input common-mode voltage output description output voltage power required signal transformer carrier frequency range input voltage range input impedance input common mode voltage output description output voltage power required 360- 1000 hz 700 v peak synchro z in (z so ) resolver z ln 180 ? 100k ? - 30k ? 20k ? 30k ? 47 - 440 hz 80 - 138 v rms; 115 v rms nominal resistive 600 k ? min resistive 500 v rms transformer isolated +r (in phase with rh-rl) and - r (in phase with rl- rh) derived from op-amps. short circuit proof. 3.0 v nominal riding on ground reference v. output voltage level tracks input level. 4 ma typ, 7 ma max from +15 v supply. 47 - 440 hz 10 - 100 v rms l-l; 90 v rms l- l nominal 148 k ? min l-l balanced resistive 500 v rms transformer isolated resolver output, - sine (- s) + cosine (+c) derived from op-amps. short circuit proof. 1.0 v rms nominal riding on ground reference v. output voltage level tracks input level. 4 ma typ, 7 ma max from +15 v supply. note: (1) pin programmable. (2) see table 6. 30 90 150 210 270 330 360 (degrees) ccw in phase with rl-rh of converter and r2-r1 of cx. 0 s1-s3 = v sin max s3-s2 = v sin( + 120) max s2-s1 = v sin( + 240) max - v max + v max 30 90 150 210 270 330 360 (degrees) ccw in phase with rh-rl of converter and r2-r4 of rx. 0 s2-s4 = v cos max s1-s3 = ?v sin( ) max - v max + v max standard synchro control transmitter (cx) outputs as a function of ccw rotation from electrical zero (ez). figure 2. synchro and resolver signals standard resolver control transmitter (rx) outputs as a function of ccw rotation from electrical zero (ez) with r2-r4 excited. solid-state buffer input protection - transient voltage suppression the solid-state signal and reference inputs are true differential inputs with high ac and dc common rejection, so most applica- tions will not require units with isolation transformers. input impedance is maintained with power off. the current ac peak +dc common mode voltage should not exceed the values in table 1. the 90 v line-to-line systems may have voltage transients which exceed the 500 v specification. these transients can destroy the thin-film input resistor network in the hybrid. therefore, 90 v l - l solid-state input modules may be protected by installing voltage suppressors as shown. voltage transients are likely to occur whenever synchro or resolver are switched on and off. for instance, a 1000 v transient can be generated when the prima- ry of a cx or tx driving a synchro or resolver input is opened. see figure 3. feedback loop the feedback loop produces a digital angle which tracks the analog input angle to within the specified accuracy of the con-
verter. the control transformer performs the following trigono- metric computation: sin( - ) = sin cos - cos sin where is the angle representing the resolver shaft position, and is the digital angle contained in the up/down counter. the track- ing process consists of continually adjusting to make ( - ) ! 0, so that will represent the shaft position . the output of the demodulator is an analog dc level proportional to sin( - ) . the error processor receives its input from the demodulator and inte- grates this sin( - ) error signal which then drives a voltage- controlled oscillator (vco). the vco?s clock pulses are accu- mulated by the up/down counter. the velocity voltage accuracy, linearity and offset are determined by the quality of the vco. functionally, the up/down counter is an incremental integrator. therefore, there are two stages of integration which make the converter a type ii tracking servo. in a type ii servo, the vco always settles to a counting rate which makes d /dt equal to d /dt without a lag. the output data will always be fresh and available as long as the maximum tracking rate of the converter is not exceeded. synthesized reference the synthesized reference section of the sdc-14560 eliminates errors caused by quadrature voltage. due to the inductive nature of synchros and resolvers, their signals lead the reference signal (rh and rl) by about 6. when an uncompensated reference signal is used to demodulate the control transformer?s output, quadrature voltages are not completely eliminated. in a 12- or 14-bit converter it is not necessary to compensate for the refer- ence signal?s phase shift. a 6 phase shift will, however, cause problems for the one minute accuracy converters. as shown in figure 1, the converter synthesizes its own cos( t + ) refer- ence signal from the sin cos( t + ), cos cos( t + ) signal inputs and from the cos t reference input. the phase angle of the synthesized reference is determined by the signal input the reference input is used to choose between the +180 and -180 phases. the synthesized reference will always be exactly in phase with the signal input, and quadrature errors will therefore be eliminated. the synthesized reference circuit also eliminates the 180 false error null hangup. quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. a digital position error will result due to the interaction of this quadrature voltage and a reference phase shift between the converter signal and reference inputs. the magni- tude of this error is given by the following formula: error = quad/f.s. signal * tan( ) where: error is in radians quad/f.s. signal is per unit quadrature input level. = signal to reference phase shift in degrees. a typical example of the magnitude of this source of error is as follows: quad/f.s. signal = .001 = 6 error = 0.35 min 1 lsb in the 16th bit. note: quad/f.s. is composed of static quadrature which is spec- ified by the resolver or synchro supplier plus the speed voltage which is given by: speed voltage = rotational speed/carrier frequency where: speed v oltage is the per unit ratio of electrical rotational speed in rps divided by carrier frequency in hz. this error is totally negligible for up to 14-bit converters. for 16- bit converters, where the highest accuracy possible is needed and where the quadrature and phase shift specifications can be higher, this source of error could be significant. the reference synthesizer circuit in the converter which derives the reference from the input signal essentially sets to zero resulting in com- plete rejection of the quadrature. digital interface the digital interface circuitry has three main functions: to latch the output bits during an inhibit command so that the stable data can be read; to furnish both parallel and three-state data formats; and to act as a buffer between the internal cmos logic and the external ttl logic. in the sdc-14560, applying an inhibit command will lock the data in the transparent latch without interfering with the continu- ous tracking of the feedback loop. therefore, the digital angle is always updated, and the inhibit can be applied for an arbitrary amount of time. the inhibit transparent latch and the 50 ns delay are part of the inhibit circuitry. the inhibit circuitry is described in detail in the logic input/output section. logic input/output logic angle outputs consist of 10, 12, 14 or 16 parallel data bits and converter busy (cb). all logic outputs are short-circuit proof to ground and +5 volts. the cb output is a positive, 0.4 to 1.0 s pulse. data changes about 50 ns after the leading edge of the pulse because of an internal delay. data is valid 0.2 s after the leading edge of cb, the angle is determined by the sum of the bits at logic ?1?. digital outputs are three-state and two bytes wide; bits 1-8 (msbs) are enabled by the signal em, bits 9-16 4 data device corporation www.ddc-web.com sdc-14560 q-10/03-0 hybrid s3 s2 s1 rh rl cr1 cr2 s1 for 90 v synchro inputs 1n6071a cr3 s2 s3 hybrid s3 s2 s1 s4 for 90 v resolver inputs cr4 cr5 s3 s2 s1 s4 90 v l-l resolver input figure 3. connections for voltage transient suppressors cr4 and cr5 are 1n6136a, bipolar transient voltage suppressors or equivalent. cr1, cr2, and cr3 are 1n6136a, bipolar transient voltage suppressors or equivalent.
(lsbs) are enabled by the signal el. outputs are valid (logic ?1? or ?0?) 150 ns max after setting em or el low, and are high impedance within 100 ns max of setting em or el high. both em and el are internally pulled-up to +5 v at 30 a max. the inhibit (inh) input locks the transparent latch so the bits will remain stable while data is being transferred (see figure 1). the output is stable 0.5 s after inh is driven to logic ?0?, see figure 4. a logic ?0? at the t input latches the data, and a logic ?1? applied to t will allow the bits to change. the inhibit transpar- ent latch prevents the transmission of invalid data when there is an overlap between cb and inh. while the counter is not being updated, cb is at logic ?0? and the inh latch is transparent. when cb goes to logic ?1? the inh latch is locked. if cb occurs after inh has been applied, the latch will remain locked and its data will not change until cb returns to logic ?0?; if inh is applied during cb, the latch will not lock until the cb pulse is over. the purpose of the 50 ns delay is to prevent a race condition between cb and inh where the up-down counter begins to change as an inh is applied. whenever an input angle change occurs, the converter changes the digital angle in 1 lsb steps and gener- ates a converter busy pulse. output data change is initiated by the leading edge of the cb pulse, delayed by 50 ns, nominal. valid data is available at the outputs 0.2 s after the leading edge of cb, see figure 5. resolution control resolution control is via two logic inputs, a and b. the resolution can be changed during converter operation so the appropriate resolution and velocity dynamics can be changed as needed. to ensure that no race conditions exist between counting and changing the resolution, inputs a and b are latched internally on the trailing edge of cb, as illustrated in figure 6. digital angle outputs are buffered and are provided in a two byte format. the first byte always contains the msbs (bits 1-8) and is enabled by placing em (pin 26) to logic ?0?. depending on the user-programmed resolution, the second byte will have bits 9 through 10, 9 through 12, or 9 through 14, while operating at 10-, 12-, or 14-bit resolution, respectively. placing el (pin 25) to logic ?0? enables the second byte, the lsbs. a logic ?0? will be present on all the unused least significant bits. table 2 lists the deg/bit for the digital angle outputs. built-in-test the built-ln-test output (bit) monitors the level of error (d) from the demodulator. d represents the difference in the input and output angles and ideally should be zero; if it exceeds approxi- mately 65 lsbs (of the selected resolution) the logic level at bit will change from a logic 1 to logic 0. this condition will occur dur- ing a large step and reset after the converter settles out. bit will also change to logic 0 for an over-velocity condition, because the converter loop cannot maintain input-output or if the converter malfunctions where it cannot maintain the loop at a null. bit will also be set if a total loss-of-signal (los) and/or a loss-of- reference (lor) occurs. dynamic performance a type ii servo loop (kv = ) and very high acceleration constants give the sdc-14560 superior dynamic performance, as listed in table 2. if the power supply voltages are not the 15 v dc nom- inal values, the specified input rates will increase or decrease in proportion to the fractional change in voltage. a control loop block diagram is shown in figure 7, and an open loop bode plot is shown in figure 8. the values of the transfer function coefficients are shown in table 3. an inhibit input, regardless of its duration, does not affect the con- verter update. a simple method of interfacing to a computer asyn- chronously to cb is: (a) apply the inhibit, (b) wait 0.5 s min., (c) transfer the data and (d) release the inhibit. 5 data device corporation www.ddc-web.com sdc-14560 q-10/03-0 14b 0 s min cb 0.1 s min figure 6. resolution control timing diagram depends on d /dt 0.4-1.0 s cb 0.2 s data valid 6.1 s min figure 5. converter busy timing diagram data valid 0.5 s asynchrous to cb inh figure 4. inhibit timing diagram table 2. digital angle outputs bit deg/bit min/bit 1 msb 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 180.0 90.0 45.0 22.5 11.25 5.625 2.813 1.406 0.7031 0.3516 0.1758 0.0879 0.0439 0.0220 0.0110 0.0055 10800.0 5400.0 2700.0 1350.0 675.0 337.5 168.75 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33 note: em enables the msbs and el enables the lsbs.
as long as the converter maximum tracking rate is not exceed- ed, there will be no lag in the converter output. if a step input occurs, as when the power is initially applied, the response will be critically damped. figure 9 shows the response to a step input. after initial slewing at the maximum tracking rate of the converter, there is one overshoot (which is inherent in a type ii servo). the overshoot settling to final value is a function of the small signal settling time. for velocity output, the simple filter shown in figure 10 will eliminate the one overshoot for step velocity input and will filter the carrier frequency ripple. analog outputs the analog outputs are velocity (vel) and ac error (e). both out- puts can swing 10 v min. with respect to ground when the volt- age level of the 15 v power supplies are 15 v. the output level range changes proportionally if the power supply levels are not at 15 v. the ac error, e, is proportional to the error ( - ) with a scaling of 50 mv/lsb (10-bit mode), 25 mv/lsb (12-bit mode) 12.5 mv/ lsb (14-bit mode), and 6.3 mv/lsb (16-bit mode). velocity out- put characteristics are listed in table 4. 6 data device corporation www.ddc-web.com sdc-14560 q-10/03-0 output 91k vel (pin 23) 0.1 f rc = 1/a figure 10. velocity filter error processor input open loop transfer function = output where: 2 a = a a 1 2 velocity out digital position out ( ) vco ct s a + 1 1 b s s + 1 10b h = 1 s a + 1 1 b 2 s s + 1 10b + - e a 2 s 2.75 4 ba bw (rad/sec) overshoot small signal settling time max slope equals tracking rate ( slew rate ) 2 1 settling time figure 9. response to a step input figure 8. open loop bode plot figure 7. control loop block diagram table 3. dynamic characteristics parameter units bandwidth 400 hz 60 hz resolution input frequency tracking rate bandwidth k a a1 a2 a b acc-1 lsb lag settling time bits hertz rps min hertz 1/sec 2 nom 1/sec nom 1/sec nom 1/sec nom 1/sec nom deg/sec 2 nom ms max 10 12 14 16 360-1000 160 40 10 2.5 220 * 54 * 81.2k * 12500 * 2.0 * 0.31 * 40k * 40k * 285 * 112 * 52 * 52 * 28.4k 7.1k 275 69 160 160 300 800 10 12 14 16 47-1000 40 10 2.5 0.61 40 * 14 * 3k * 780 * 0.29 * 0.078 * 10k * 10k * 55 * 28 * 13 * 13 * 1k 264 17.2 4.3 350 550 1400 3400 note: * means the same as value to the left.
velocity output the velocity output (vel) from the sdc-14560 is a dc voltage proportional to angular velocity d /dt = d /dt. the velocity input is the second integrator, as shown in figure 7. its linearity is dependent solely on the linearity of the voltage controlled oscil- lator (vco). due to the highly linearized vel output, the electro- mechanical tachometer can now be eliminated from motion con- trol systems. bandwidth (bw) and the acceleration constant (k a ) can be determined from the formulas shown: bw(hz) = bw(rad/sec)/2 k a = a 2 outputs e and vel are not required for normal operation of the converter. v is used as an internal dc reference with the direct input option. maximum loading on v is 40k ohm; maximum load- ing for e and vel is 3k ohm. the velocity characteristics are shown in tables 4 and 5. output e is not closely controlled or characterized. consult the factory for further information. figures 11, 12, 13 are the synchro, resolver, and direct input connection diagrams, respectively. 7 data device corporation sdc-14560 q-10/03-0 reference oscillator parallel data sdc-14565/4/6 stator rotor s3 s1 s2 s2 s1 s3 r4 r2 lo hi rh vel (velocity) inh (inhibit) cb (count) rl s4 s4 el em reference oscillator parallel data sdc-14567/8/9 stator rotor sin cos s2 s1 s3 r4 r2 lo hi rh vel (velocity) inh (inhibit) cb (count) rl v s4 el em figure 12. resolver input connection diagram figure 13. direct input connection diagram table 4. velocity characteristics parameter units standard hi lin typ max typ max polarity output voltage voltage scaling scale factor scale factor tc reversal error reversal error tc linearity linearity tc zero offset zero offset tc load v rps/10 v % ppm/c % ppm/c % output ppm/c mv v/c kohm table 5. velocity voltage scaling bw resolution (values in rps/volt) 10 12 14 16 hl lo 16 4 4 1 1 0.25 0.25 0.063 note: if the resolution is changed while the input is changing, then the velocity output voltage and the digital output will have a transient until it settles to the new velocity scaling at a speed determined by the bandwidth. if additional information is required consult the factory. reference oscillator parallel data sdc-14560/1/2/3 stator rotor s3 s1 s2 s2 s1 s3 el em r2 r1 lo hi rh vel (velocity) inh (inhibit) cb (count) rl figure 11. synchro input connection diagram table 6. overall accuracy (min.) vs. resolution accuracy grade (minutes) resolution programmed to: 10 bit 12 bit 14 bit 16 bit 1 +1 lsb 2 + 1 lsb 4 + 1 lsb 6 + 1 lsb 22.1 23.1 25.1 27.1 6.3 7.3 9.3 11.3 2.3 3.3 5.3 7.3 1.3 2.3 4.3 6.3 positive for increasing angle. 13 10min 13 10min see voltage scaling table 5. 10 15 10 15 100 200 100 200 1 2 0.5 0.7 25 50 25 50 1 2 0.5 0.7 25 50 25 50 15 40 15 40 25 50 25 50 - 3 min - 3 min
ct mode the sdc-14560 can also be used as a solid-state control transformer. this is analogous to the function of the rotary con- trol transformer except here the rotary shaft input is replaced by a digital angle. referring to the equation below, the output is an ac voltage (e) which varies as the sine of the difference between the analog input angle and the digital angle. e = sin( - )cos t control transformers are frequently used as error signal genera- tors in closed servo loops. they are useful when digital remote control of a position servo must be accomplished. figure 14 illustrates a block diagram of the control transformer (ct) mode. the procedure to enable this function is to disable the up-down counter by setting s (pin 30) to logic ?0? and using the digital output lines (which are bidirectional) as dig- ital inputs. when the converter is functioning as a ct, the digital inputs are double buffered,em is redefined as lm (latch msbs), el is redefined as ll (latch lsbs) and inh becomes la (latch all). data should be valid for the time any latch is enabled. see figure?s 16 & 17 for timing diagrams. transformers figure 15 illustrates the transformer connection diagram. these transformers are designed for the voltage follower buffer input option to the sdc-14560. however, the reference trans- formers may also be used with the solid-state buffer input options. passive transformers are considerably larger in size for 60 hz than for 400 hz. to minimize size, active transformers are utilized over passive devices for 60 hz. these active 60 hz transformers have op-amp outputs and require connection to a +15 v power supply. 8 data device corporation www.ddc-web.com sdc-14560 q-10/03-0 s1 s2 s3 solid state synchro input option electronic scott t sin cos s1 s2 s3 solid state resolver input option resolver conditioner sin cos s4 solid state resolver input option voltage follower buffer sin cos sin cos input options v internal dc reference reference conditioner synthesized ref demod bit detect high accuracy control transformer input option 16 bit ct transparent latch 16 bit u-d counter (set mode) power supply conditioner resolver input +5 v lm(em) resolution control +10 v internal dc ref v (+5 v) +15 bit e d r gain e sin ( - ) rl rh sin cos ab diff gain of 2 ll(el) +15 v -15 v 1-8 9-16 la(inh) digital angle set figure 14. ct mode block diagram 1 3 5 11 15 10 20 t1a 6 t1b 16 s1 s3 s2 sdc-14567 sdc-14569 s c v 1 3 2 synchro input 1 3 11 15 10 20 t1a 6 t1b 16 s1 s3 s2 sdc-14567 sdc-14569 s c v 1 3 2 resolver input s4 400 hz resolver transformer t1 21046 or 21047 or 21048 400 hz synchro transformer t1 21044 or 21045 s3 s2 s1 +15 -s -vs 24126 v s3 s2 sdc-14568 s c v 1 3 2 synchro input 400 hz ref transformer 21049 60 hz synchro transformer 24126 s1 +15 v +c gnd t2 rh sdc-14567 rh rl 20 19 synchro input rl sdc-14569 10 6 +15 v rh rl v -r 24133 +r +15 gnd sdc-14568 19 20 ref input 60 hz ref transformer 24133 rh rl v rh rl 1 5 1 figure 15. transformer connection diagram
9 data device corporation www.ddc-web.com sdc-14560 q-10/03-0 400 ns min. (t inh) transparent latched (data in) 1-16 bits 100 ns min. data changing data stable la ( inh ) lm ( em ), ll ( el ) data changing data stable 100 ns min. 100 ns min. 400 ns min. 200 ns min. 200 ns min. ll lm ( em ) la ( inh ) (8 bit data bus in) bits (9-16) bits (1-8) ( el ) figure 16. ll, lm, la timing diagram (16-bit) figure 17. ll, lm, la timing diagram (8-bit)
10 data device corporation www.ddc-web.com sdc-14560 q-10/03-0 bottom views 0.81 max (20.57) 0.30 max (7.62) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.105 0.005 (2.67 0.13) 1 345 109876 11 12 14 15 20 19 18 17 16 pin numbers for ref. only dot on top face identifies pins 1 and 11. t1a and t1b pairing numbers listed in short side. marking includes part number and t1a and t1b. terminals 0.25 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder plated brass t1a t1b 1 5 3 6 10 11 15 16 20 t1a t1b synchro input resolver output to converter v (-sin) +sin v (-cos) +cos s1 s3 s2 1 3 6 10 11 15 16 20 t1a t1b resolver input resolver output to converter v (-sin) +sin v (-cos) +cos s1 s3 s2 s4 0.81 max (20.57) 0.30 max (7.62) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.105 0.005 (2.67 0.13) 123 5 109876 pin numbers for ref. only. dot on top face identifies pin 1. marking includes part number. terminals 0.25 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder plated brass 1.14 max (28.96) case is black and non-conductive 1.14 max (28.96) * s1 * s3 (+15 v) +15 v (-r) -s + * * (rh) s2 (rl) + * (v) v (+r) +c (-vs) -vs 24126 or (24133) 0.21 0.3 (5.33 0.76) 0.85 0.010 (21.59 0.25) 0.175 0.010 (4.45 0.25) noncumulative tolerance 0.040 0.002 dia. pin. solder plated brass 0.42 (10.67) max. 0.25 (6.35) min. (bottom view) 0.13 0.03 (3.30 0.76) 1 5 6 10 reference input output to converter rh rl rh rl these external transformers are for use with converter modules with voltage follower buffer inputs. 400 hz synchro and resolver transformer diagrams (tia and tib) each transformer consists of two sections, tia and tib 1. mechanical outlines 2.schematic diagrams a. synchro (21044, 21045) b. resolver (21046, 21047, 21048) the mechanical outline is the same for the synchro input trans- former (24126) and the reference input transformer (24133), except for the pins. pins for the reference transformer are shown in parenthesis ( ) below. an asterisk * indicates that the pin is omitted. 400 hz reference transformer diagrams (t2) 2.schematic diagram 1. mechanical outline 60 hz synchro and reference transformer diagrams figure 18. transformer mechanical outlines
11 data device corporation www.ddc-web.com sdc-14560 q-10/03-0 1.895 0.005 (48.1 0.13) 1.700 0.005 (43.2 0.13) 0.018 (0.46) diam typ 0.100 typ(2.54) tol. non- cumulative 0.21 max (5.3) dot identifies pin 1 0.775 0.005 (19.7 0.13) 0.600 0.005 (15.2 0.13) 0.09 0.01 (2.3 0.25) 0.10 0.01 (2.5 0.3) side view bottom view 0.24 min (6.4) 0.015 max (0.39) seating plane 0.055 (1.4) rad typ 0.086 typ radius notes: 1. dimensions shown are in inches (mm). 2. lead identification numbers are for reference only. 3. lead cluster shall be centered within 0.01(0.25) of outline dimensions. lead spacing dimensions apply only at seating plane. 4. pin material meets solderability requirements to mil-std-202e, method 208c. 5. case is electrically floating. figure 19. sdc-14560 mechanical outline 36-pin ddip (kovar) table 7. sdc-14560 pin connection/functions pin no. function pin no. function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 s1(r) s1(s) v(x) s2(r) s2(s) +c(x) s3(r) s3(s) +s(x) s4(r) - - 1 (msb) 2 3 4 5 6 7 8 9 10 (lsb 10-bit mode) 11 12 (lsb 12-bit mode) 13 14 (lsb 14-bit mode) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 b a bit inh +15 v -15 v s gnd +5 v e em el cb vel 16 (lsb 16-bit mode) 15 rl rh note: ?(r)? means resolver, ?(s)? means synchro, and ?(x)? means direct.
12 data device corporation www.ddc-web.com ordering information sdc-1456x-xxxx supplemental process requirements: s = pre-cap source inspection l = 100% pull test q = 100% pull test and pre-cap source inspection k = one lot date code w = one lot date code and precap source inspection y = one lot date code and 100% pull test z = one lot date code, precap source inspection and 100% pull test blank = none of the above accuracy: 2 = 4 minutes + 1 lsb 4 = 2 minutes + 1 lsb 5 = 1 minute + 1 lsb process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data configuration: 0 = 11.8 v, 400 hz, synchro 1 = 90 v, 400 hz, synchro 2 = 90 v, 60 hz, synchro 3 = 11.8 v, 400 hz, synchro, hi lin velocity 4 = 26 v, 400 hz, resolver 5 = 11.8 v, 400 hz, resolver 6 = 11.8 v, 400 hz, resolver, hi lin velocity 7 = 1 v, 400 hz, direct resolver 8 = 1 v, 60 hz, direct resolver 9 = 1 v, 400 hz, direct resolver, hi lin velocity *standard ddc processing with burn-in and full temperature test ? see table below. sdc-14560 q-10/03-0
13 type freq. ref. voltage l-l voltage ref. xfmr signal xfmr synchro synchro resolver resolver resolver synchro? 400 hz 400 hz 400 hz 400 hz 400 hz 60 hz 115 v 26 v 115 v 26 v 26 v 115 v 90 v 11.8 v 90 v 26 v 11.8 v 90 v 21049 21049 21049 21049 21049 24133-1 24133-3 21045* 21045* 21048* 21047* 21046* 24126-1 24126-3 part numbers * the part number for each 400 hz synchro or resolver isolation transformer includes two separate modules as shown in the outline drawings. ? 60 hz synchro transformers are available in two temperature ranges: 1 = -55c to +105c 3 = 0c to +70c transformer ordering information table 1 1015, 1030* burn-in 3000g 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal ? 2009, 2010, 2017, and 2032 inspection condition(s) method(s) test mil-std-883 standard ddc processing * when applicable data device corporation www.ddc-web.com sdc-14560 q-10/03-0
14 q-10/03-0 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u printed in the u.s.a. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7771 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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